603 Hardware Specifications, REV 2 7
Preliminary—Subject to Change without Notice
Figure 1. SYSCLK Input Timing Diagram
1.3.2.2 Input AC Specifications
Table 6 provides the input AC timing specifications for the 603 as defined in Figure 2 and Figure 3. These
specifications are for 25, 33.33, 40, 50, and 66.67 MHz bus clock (SYSCLK) frequencies
.
8 SYSCLK
short- and
long-term jitter
—
±
150 —
±
150 —
±
150 —
±
150 —
±
150 ps 2
9 603 internal
PLL relock time
— 100 — 100 — 100 — 100 — 100
µ
s 3,4
Notes
: 1. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
2. This is the sum total of both short- and long-term jitter, and is guaranteed by design.
3. Timing is guaranteed by design and characterization, and is not tested.
4. PLL relock time is the maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are reached
during the power-on reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET
must be held asserted for a minimum of 255
bus clocks after the PLL relock time (100
µ
s) during the power-on reset sequence.
5.
Caution
: The SYSCLK frequency and PLL_CFG0–PLL_CFG3 settings must be chosen such that the resulting
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective
maximum or minimum operating frequencies. Refer to the PLL_CFG0–PLL_CFG3 signal description in Section 1.7,
“System Design Information,” for valid PLL_CFG0–PLL_CFG3 settings, and to Section 1.8, “Ordering Information,”
for available frequencies and part numbers.
Table 5. Clock AC Timing Specifications (Continued)
Vdd = 3.3
±
5% V dc, GND = 0 V dc
,
0
≤
T
J
≤
105
°C
Num Characteristic
25 MHz 33.33 MHz 40 MHz 50 MHz 66.67
Unit Notes
Min Max Min Max Min Max Min Max Min Max
VM
CVil
CVih
SYSCLK
VM = Midpoint Voltage (1.4 V)
2 3
1
