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PM5358 S/UNI-4x622 Driver Manual
Proprietary and Confidential to PMC-Sierra, Inc. 11
Document ID: PMC-2010419, Issue 1
LIST OF TABLES
Table 1: S/UNI-4x622 Module Initialization Vector: sSUNI4x622_MIV.............................27
Table 2: S/UNI-4x622 Device Initialization Vector: sSUNI4x622_DIV ..............................27
Table 3: S/UNI-4x622 Section Overhead (SOH) ISR Mask:
sSUNI4x622_MASK_ISR_SOH ................................................................................29
Table 4: S/UNI-4x622 Line Overhead (LOH) ISR Mask:
sSUNI4x622_MASK_ISR_LOH.................................................................................29
Table 5: S/UNI-4x622 Receive Path Overhead (RPOH) ISR Mask:
sSUNI4x622_MASK__ISR_RPOH............................................................................30
Table 6: S/UNI-4x622 ISR Mask: sSUNI4x622_MASK_ISR_PYLD .................................31
Table 7: S/UNI-4x622 ISR Mask: sSUNI4x622_MASK_ISR_FIFO ..................................31
Table 8: S/UNI-4x622 Module Data Block: sSUNI4x622_MDB ........................................33
Table 9: S/UNI-4x622 Device Data Block: sSUNI4x622_DDB .........................................34
Table 10: S/UNI-4x622 Input/Output Configuration: sSUNI4x622_CFG_GLOBAL..........36
Table 11: S/UNI-4x622 Channel Configuration: sSUNI4x622_CFG_CHAN.....................36
Table 12: S/UNI-4x622 Section Overhead Configuration:
sSUNI4x622_CFG_SOH...........................................................................................37
Table 13: S/UNI-4x622 Line Overhead Configuration: sSUNI4x622_CFG_LOH .............37
Table 14: S/UNI-4x622 Receive Path Overhead Configuration:
sSUNI4x622_CFG_RPOH ........................................................................................38
Table 15: S/UNI-4x622 Transmit Path Overhead Configuration:
sSUNI4x622_CFG_TPOH.........................................................................................38
Table 16: S/UNI-4x622 Payload Processor: sSUNI4x622_CFG_PYLD...........................40
Table 17: S/UNI-4x622 FIFO Configuration: sSUNI4x622_CFG_FIFO............................41
Table 18: S/UNI-4x622 Clock Interface Configuration: sSUNI4x622_CFG_CLK .............41
Table 19: S/UNI-4x622 Clock Interface Configuration:
sSUNI4x622_CFG_RALRM......................................................................................42
Table 20: S/UNI-4x622 Line Interface Configuration:
sSUNI4x622_CFG_INTF_LINE.................................................................................42
Table 21: S/UNI-4x622 Global System Interface Configuration:
sSUNI4x622_CFG_INTF_SYS_GLOBAL.................................................................43