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6: The Bus Interface
ARM720T CORE CPU MANUAL EPSON 6-3
6.2 Bus interface signals
The signals in the ARM720T processor bus interface can be grouped into the following
categories:
Transfer type HTRANS[1:0]
See
Transfer types
on page 6-5.
Address and control
HADDR[31:0]
HWRITE
HSIZE[2:0]
HBURST[2:0]
HPROT[3:0]
See
Address and control signals
on page 6-7.
Slave transfer response
HREADY
HRESP[1:0]
See
Slave transfer response signals
on page 6-9.
Data
HRDATA[31:0]
HWDATA[31:0]
See
Data buses
on page 6-10.
Arbitration
HBUSREQ
HGRANT
HLOCK
See
Arbitration
on page 6-12.
Clock
HCLK
HCLKEN
See
Bus clocking
on page 6-13.
Reset
HRESETn
See
Reset
on page 6-13.
Each of these signal groups shares a common timing relationship to the bus interface cycle.
All signals in the ARM720T processor bus interface are generated from or sampled by the
rising edge of HCLK.