Embedded Intel® Atom Processor D2700 with Intel® NM10 Express Chipset
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5.4 Port 80h POST Codes
During the POST, the BIOS generates diagnostic progress codes (POST codes) to I/O
port 80h. If the POST fails, execution stops and the last POST code generated is left at
port 80h. This code is useful for determining the point at which an error occurred.
Displaying the POST codes requires a PCI bus add-in card, often called a POST card.
The POST card can decode the port and display the contents on a medium such as a
seven-segment display.
NOTE
The POST card must be installed in the PCI bus connector.
The following tables provide information about the POST codes generated by the BIOS:
Table 43 lists the Port 80h POST code ranges
Table 44 lists the Port 80h POST codes themselves
Table 45 lists the Port 80h POST sequence
NOTE
In the tables listed above, all POST codes and range values are listed in hexadecimal.
Table 43. Port 80h POST Code Ranges
Entering SX states S0 to S5.
Resuming from SX states (0x10 0x20 S2, 0x30 S3, etc.)
PEI phase pre MRC execution
PEI phase post MRC execution
CPU Initialization (PEI, DXE, SMM)
I/O Buses: PCI, USB, ATA etc. 0x5F is an unrecoverable error. Start with PCI.
Output devices: All output consoles.
Input devices: Keyboard/Mouse.
Boot Devices: Includes fixed media and removable media. Not that critical since
consoles should be up at this point.
