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5-78 C141-E050-02EN
Both the host and device perform a CRC function during an Ultra DMA burst. At
the end of an Ultra DMA burst the host sends the its CRC data to the device. The
device compares its CRC data to the data sent from the host. If the two values do
not match the device reports an error in the error register at the end of the
command. If an error occurs during one or more Ultra DMA bursts for any one
command, at the end of the command, the device shall report the first error that
occurred.
5.5.2 Phases of operation
An Ultra DMA data transfer is accomplished through a series of Ultra DMA data
in or data out bursts. Each Ultra DMA burst has three mandatory phases of
operation: the initiation phase, the data transfer phase, and the Ultra DMA burst
termination phase. In addition, an Ultra DMA burst may be paused during the
data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for
each of these phases, 5.6.4 defines the specific timing requirements). In the
following rules DMARDY- is used in cases that could apply to either
DDMARDY- or HDMARDY-, and STROBE is used in cases that could apply to
either DSTROBE or HSTROBE. The following are general Ultra DMA rules.
a) An Ultra DMA burst is defined as the period from an assertion of DMACK-
by the host to the subsequent negation of DMACK-.
b) A recipient shall be prepared to receive at least two data words whenever it
enters or resumes an Ultra DMA burst.
5.5.2.1 Ultra DMA burst initiation phase
a) The Ultra DMA burst initiation phase is started by the assertion of DMARQ
signal by the device, and is ended when the transmitting side has inverted
STROBE signal for transmitting the first data.
b) The Ultra DMA burst requires the assertion of DMARQ signal by the device.
c) The host asserts DMACK-signal when it is able to start the requested burst.
d) The host always asserts DMACK signal after detecting the first assertion of
DMARQ signal.
e) Ultra DMA data in burst
The device starts transmission of the data to DD (15 : 0) when;
• DMACK-signal assertion has been detected,
• STOP signal negation has been detected, or
• HDMARDY-signal assertion has been detected.
f) Ultra DMA data out burst
The device should not invert the state of this signal in the period from the
moment of DMARQ signal assertion or DDMARDY-signal assertion to the
moment of inversion of the first STROBE signal.