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5-90 C141-E050-02EN
Note: Since no bit clock is available, the recommended approach for
calculating CRC is to use a word clock derived from the bus strobe. The
combinational logic shall then be equivalent to shifting sixteen bits serially
through the generator polynominal where DD0 is shifted in first and DD15 is
shifted in last.
Figure 5.8 An example of generation of parallel CRC
Table 5.14 Parallel generation equation of CRC polynomial
CRCINO=f
16
CRCIN8 = f
8
XOR f
13
CRCIN1=f
15
CRCIN9 = f
7
XOR f
12
CRCIN2=f
14
CRCIN10 = f
6
XOR f
11
CRCIN3=f
13
CRCIN11 = f
5
XOR f
10
CRCIN4=f
12
CRCIN12 = f
4
XOR f
9
XOR f
16
CRCIN5=f
11
XOR f
CRCIN13 = f
3
XOR f
8
XOR f
15
CRCIN6=f
10
XOR f
15
CRCIN14 = f
2
XOR f
7
XOR f
14
CRCIN7=f
9
XOR f
14
CRCIN15 = f
1
XOR f
6
XOR f
13
f
1
= DD0 XOR CRCOUT
15
f
9
= DD8 XOR CRCOUT7 XOR f
5
f
2
= DD1 XOR CRCOUT
14
f
10
= DD9 XOR CRCOUT6 XOR f
6
f
3
= DD2 XOR CRCOUT
13
f
11
= DD10 XOR CRCOUT5 XOR f
7
f
4
= DD3 XOR CRCOUT
12
f
12
= DD11 XOR CRCOUT4 XOR f
1
XOR f
8
f
5
= DD4 XOR CRCOUT
11
XOR f
1
f
13
= DD12 XOR CRCOUT3 XOR f
2
XOR f
9
f
6
= DD5 XOR CRCOUT
10
XOR f
2
f
14
= DD13 XOR CRCOUT2 XOR f
3
XOR f
10
f
7
= DD6 XOR CRCOUT
9
XOR f
3
f
15
= DD14 XOR CRCOUT1 XOR f
4
XOR f
11
f
8
= DD7 XOR CRCOUT
8
XOR f
4
f
16
= DD15 XOR CRCOUT0 XOR f
5
XOR f
12
DD : Data from bust f : Feedback
CRCIN : Output of combination logic (the next CRC)
CROUT : Result of 16 bit latch (current CRC)
Combination
logic
CRCOUT
Latch
16
16
16
16
Word
clock
CRCIN
DD0–DD15
F1–f16