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ICX418ALB
Clock Switching Characteristics
∗1
When vertical transfer clock driver CXD1267AN is used.
∗2
tf ≥ tr – 2ns.
∗3
The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
Min.
two
Typ. Max.
16 20
Unit
ns
RemarksItem
Horizontal transfer clock
Symbol
Hφ1, Hφ2
∗
3
Min.
twh
Typ.
Max.
Min. Typ.
Max.
Min. Typ.
Max.
Min. Typ.
Max.
twl tr tf
2.3
11
1.5
2.5
20
5.38
13
1.8
20
5.38
51
15
0.01
0.01
3
19
0.5
0.5
15
15
0.01
0.01
3
250
19
0.5
Unit
µs
ns
ns
µs
ns
µs
Remarks
During readout
∗1
∗2
When draining
charge
Item
Readout clock
Vertical transfer
clock
Reset gate clock
Substrate clock
Symbol
VT
Vφ1, Vφ2,
Vφ
3, Vφ4
Hφ
Hφ1
Hφ2
φRG
φSUB
Horizontal
transfer clock
0.5
During
imaging
During
parallel-serial
conversion