Theory of Operation
Theory of Operation
3Ć6
Time Base Controller (TBC) A1Ă
4
Ċ The time base controller (TBC)
provides the horizontal acquisition control for the oscilloscope. It counts
pretrigger and posttrigger samples and writes data points into acquisition
memory. Programming and control of the sampler is through the TBC. CPU
access to acquisition memory is also through the TBC.
The TBC operates in three basic acquisition modes.
H In Fast mode the sampler acquires and stores the complete record
internally. When stopped, the analog data can be read out, digitized,
and moved into acquisition memory. This process is based on the
60.6 MHz oscillator (Y401).
H In Slow mode, the sampler acts as a sample and hold device. The data
points are transferred point by point to be digitized and stored in
acquisition RAM as they are acquired. This process is based on the
40.0 MHz oscillator (Y402).
H In Peak Detect mode the sampler holds the minimum and maximum
values over a sample interval. The data points are transferred point by
point to be digitized and stored in the acquisition RAM as they are
acquired.
The processor initiates the acquisition. Once ACQINIT is released and the
pretrigger count is satisfied, EPTHO (end of pretrigger holdoff) is asserted to
the trigger logic. Once the trigger logic receives the EPTHO, it will accept
triggers. A trigger from SYNTRIG A will start the posttrigger counter in the
TBC. Once the posttrigger count is finished, the sampler will be stopped.
Acquisition Memory A1Ă
4
Ċ The acquisition memory consists of an
8KĆbyĆ8K SRAM. The CPU reads this memory through the time base
controller.
The time interpolator counter in the TBC counts for the duration of the slow
ramp and terminates the count when it receives COUNTSTOP from the time
interpolator.
The holdoff counter holds off trigger from being accepted for a
programmable period of time. It is asynchronous to the FAST system clock.
HOLDOFF begins on MAT (main accepted trigger).
Time Interpolator Ċ The Time Interpolator is a dualĆramp timing circuit
that detects and measures the time difference between a trigger event and
the sample clock. The CPU uses this time to correctly place the data points
obtained on different trigger events. The TBC contains the ramp counters.
The dual ramp consists of a shortĆduration, positiveĆgoing ramp and a
longĆduration, negativeĆgoing ramp. The ramps are the result of charging or
discharging integrating capacitors C307 and C305 from constant current
sources. The charging and discharging currents are available at the
collectors of Q304 and Q305, respectively. The ratio of these currents is
about 2000 to 1.
