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The Status Model Introduction to Programming
Agilent 8163A/B, 8164A/B & 8166A/B Mainframes, Fifth Edition 37
Annotations
Status Byte Register
• Bit 3, the QSB, is built from the questionable event status register and
its enable mask.
• Bit 4, the MAV, is set if the message output queue is not empty.
• Bit 5, the ESB, is built from the SESR and its SESEM.
• Bit 7, the OSB, is built from the operation event status register and its
enable mask.
• All other bits are unused, and therefore set to 0.
Standard Event Status Register
• Bit 0 is set if an operation complete event has been received since the
last call to *ESR?.
• Bit 1 is always 0 (no service request).
• Bit 2 is set if a query error has been detected.
• Bit 3 is set if a device dependent error has been detected.
• Bit 4 is set if an execution error has been detected.
• Bit 5 is set if a command error has been detected.
• Bit 6 is always 0 (no service request).
• Bit 7 is set for the first call of *ESR? after Power On.
Operation/Questionable Status Summary
• The Operation/Questionable Status Summary consist of a condition and
an event register.
• A "rising" bit in the condition register is copied to the event register.
• A "falling" bit in the condition register has no effect on the event
register.
• Reading the condition register is non-destructive.
• Reading the event register is destructive.
• A summary of the event register and its enable mask is set in the status
byte.