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The Waveform DAC voltage reference is driven by U410B. This reference
controls the magnitude of the nominal 0 to -40 mA DAC output current.
The reference level is varied to produce 0 to -2 dB fine amplitude level
control via dc signal AMP_CTL and
2 dB of dynamic amplitude flatness
correction for static and swept frequency operation via flatness correction
dac U409. These reference voltage adjustments are summed together in
amplifier U410B. Amplitude flatness correction data are stored in
calibration memory during calibration. These data are used to produce a
modulation program with corresponding 8-bit amplitude correction data
values which are gated to latch U412 during operation. These data
provide real-time correction of the output amplitude level as frequency
changes are made. Amplifier U408 and Q401 use the waveform DAC
reference voltage to center the waveform DAC output signal near 0 volts.
U404 and U405 are the high-speed waveform RAM. Together, U404 and
U405 form a 16383 x 12-bit RAM. Each RAM stores and outputs 6 bits of
the waveform DAC 12-bit WD data bus. RAM U404 drives the least
significant 4 bits and U405 drive the most significant 8 bits of the WD
data bus. Note that DAC U407 calls D1 the most-significant bit (MSB)
and D12 it’s least-significant bit (LSB). Waveform RAM addresses are
controlled by the DDS ASIC’s WA (waveform address) bus.
Chapter 5 Theory of Operation
Waveform DAC/Amplitude Leveling/Waveform RAM
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