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Theory of Operation
VITS100 NTSC VITS Inserter Instruction Manual
4–3
samples. The outputs of U4 and U5 are multiplexed by U82 and U83 to increase
the data rate from 4
FSC
to 8
FSC
. The outputs of U82 and U83 are latched by U1
before being converted to ECL levels. U9 and U10 are the level converters for
the DAC, U65, which is located on Diagram 7. The four LSBs are latched by U3
and then selected by a multiplexer, U7 before being converted to ECL levels by
U11.
Test signal data is stored in U4, U5, and U6 in blocks of eight. The blocks of
data are addressed by the Block PROM, U13, and two test signal select lines.
When the test signal select circuitry calls for a given test signal, the Block
PROM uses V1 to determine the correct phase of subcarrier, uses “halfline” to
determine when to generate a half line, and uses the seven MSBs of horizontal
count to select the appropriate blocks of data.
Diagram 7. The U65 is a 12-bit DAC that turns the data into analog voltage levels
at an 8
FSC
rate. A one-volt reference is generated for the DAC by U84. The
analog output signal is filtered by a 7-pole filter, L12, L13, and L14, with T2
functioning as a second order group delay correction.
The signal is AC coupled to a buffer, U67, and clamped to remove any DC level
change with temperature. This allows the test signal DC level to match the
Program Video DC level very accurately.
This video buffer drives the Channel Switch, U64, which switches between
Program Video and VITS. The output of Channel Switch drives the MONITOR
OUT and the Program Output.
K2 controls the signal to the PROGRAM OUT. It switches the PROGRAM IN
through a delay line, L7, L3, and C52 to the PROGRAM OUT when the power
shuts off or when the front-panel RELAY BYPASS button is pushed. The delay
line in this bypass mode matches the time it takes for the video to travel through
the processing circuitry.
The circuitry that genlocks to the incoming program signal appears on three of
the schematic diagrams in the Diagrams section of this manual. Key circuitry is
located on diagrams 4 (Genlock), 5 (Program Input, Sync Stripper, VIRS
Detection, & Genlock A/D Input), and 6 (Clocks).
Diagram 5. U42 buffers and clamps the program input signal The output of U42
also drives the Sync Stripper, U44. U44 strips off the composite sync and
generates the backporch timing pulse used by the clamps.
Composite sync and the backporch timing are shifted to TTL levels by Q1, Q3,
VR1, and VR2. Their outputs are gated together by U57A and U57B to produce
the clamp pulse for U42.
Genlock