Mitsubishi Electronics QCPU Welding System User Manual


  Open as PDF
of 1204
 
10-19
D(P).DDRD
7
10
7
7
7
7
7
7
10.3 Reading Devices from Another CPU (D(P).DDRD)
Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an
error code is stored into SD0.
(1) Specified another CPU is wrong or the multiple CPU high-speed transmission dedicated
instruction cannot be used in the setting (Error code: 4350).
The reserved CPU has been specified.
Unmounted CPU has been specified.
The result of dividing the start I/O number of another CPU by 16n is outside the range of
3E0
H to 3E3H.
The instruction was executed without setting "Use multiple CPU high speed
transmission".
The instruction was executed with the Q02UCPU.
Host CPU has been specified.
The CPU where the instruction cannot be executed has been specified.
(2) The instruction cannot be executed with the CPU. (Error code: 4351)
Another CPU does not support this instruction.
(3) The number of devices is wrong. (Error code: 4352)
(4) The device that cannot be used for the instruction has been specified. (Error code: 4353)
(5) A device has been specified by the character string that cannot be used.(Error code: 4354)
(6) The number of read points ( +1)is other than 0 to 100. (Error code: 4355)
In any of the following cases, the instruction is completed abnormally, and an error code is
stored into a device specified at completion status storage device ( +0).
(1) The request of the instruction to the target CPU is more than the acceptable value (no empty
blocks exist in the multiple CPU high speed transmission area). (Error code: 0010
H)
(2) A device for another CPU specified at cannot be used at another CPU, or is out of device
range. (Error code: 1001H)
(3) The number of read points set with the D(P).DDRD instruction is 0. (Error code: 1081
H)
(4) The response of the instruction from another CPU cannot be returned (no empty blocks exist
in the multiple CPU high speed transmission area). (Error code: 1003
H)
S1
S1
S2