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100 www.xilinx.com SPI-4.2 Lite v4.3 User Guide
UG181 June 27, 2008
Chapter 5: Constraining the Core
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the following examples, the target performance is 340 Mbps. Please ensure that
modifications to these constraints do not create paths that are unconstrained.
Time Names for Clocks
The following Sink core clock constraints are required:
• NET “RDClk_P” TNM_NET = “RDClk_P”;
• NET "<snk_instance_name>/U0/cal0/EnRSClk_int*" TNM = FFS
snk_cal_flops;
The following Sink core user-interface-clock constraints are required when the example
design is used, and the user interface signals are looped back to the source core interface.
• NET "CalClk" TNM_NET = "CalClk";
• NET "LoopbackClk" TNM_NET = "LoopbackClk";
The following Sink core user interface clock constraints are only required when the
respective clocks are used.
• NET "SnkCalClk" TNM_NET = "SnkCalClk";
• NET "SnkFFClk" TNM_NET = "SnkFFClk";
• NET "SnkStatClk" TNM_NET = "SnkStatClk";
Timespecs for Clocks
These constraints specify the frequency and duty cycle of the clock signal. For high
frequency clocks, clock jitter is also specified. These values can be modified according to
user design.
The following Sink core clock constraints are always required. The generated SPI-4.2 Lite
core may have different timing constraints than the examples provided.
• TIMESPEC "TS_RDClk_P" = PERIOD "RDClk_P" 170MHz HIGH 50%
INPUT_JITTER 300ps;
• TIMESPEC "TS_SnkCalFlops" = FROM "snk_cal_flops" TO
"snk_cal_flops" "TS_RDClk_P"/ 4;
The following Sink core user interface clock constraints are required when the example
design is used, and the user interface signals are looped back to the source core interface.
• TIMESPEC "TS_CalClk" = PERIOD "CalClk" 43MHz HIGH 50%;
• TIMESPEC "TS_LoopbackClk" = PERIOD "LoopbackClk" 170MHz HIGH
50% INPUT_JITTER 300ps;
The following Sink core user interface clocks constraints are only required when the
respective clocks are used.
• TIMESPEC "TS_SnkCalClk" = PERIOD "SnkCalClk" 43MHz HIGH 50%;
• TIMESPEC "TS_SnkFFClk" = PERIOD "SnkFFClk" 170MHz HIGH 50%
INPUT_JITTER 111ps;
• TIMESPEC "TS_SnkStatClk" = PERIOD "SnkStatClk" 43MHz HIGH 50%;
Maxdelay for Reset
The following Sink core reset signal constraints are always required. Once generated, the
SPI-4.2 Lite core may have different timing constraints than the examples provided below.