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102 www.xilinx.com SPI-4.2 Lite v4.3 User Guide
UG181 June 27, 2008
Chapter 5: Constraining the Core
R
• INST "<snk_instance_name>/U0/clk0/rdclk_dcm0" IOBDELAY_VALUE =
0;
Placement Constraints
Although the SPI-4.2 Lite core does not require fixed pinouts, there are several placement
constraints that are critical to meet performance requirements and process through the
Xilinx tools. The constraints generated in the CORE Generator system is only an example
and should be modified. The user can modify these constraints to:
• Move the core placement to a different area
• Target a different device (other than the example device package configuration)
See Constraints Migration Guide for information on how to migrate the core to a different
area or device-package.
I/O Placement
In SPI-4.2 Lite core, the user has the flexibility to place the SPI-4.2 Lite I/Os according to
their needs. The user is not restricted to place the I/Os in the bank options provided in the
GUI. The placement of the I/Os can be defined using 2 kinds of constraints: bank or pin-
lock constraints.
The following is an example of how to define I/O bank constraints:
• INST "RCtl*" LOC = "Bank5"; # 1 LVDS I/O pair
• INST "RDat*" LOC = "Bank5"; # 16 LVDS I/O pairs
Note that all the SPI-4.2 Lite I/Os do not need to be in a single bank as given in the example
UCF. Ensure that there are enough I/Os in the targeted bank (or banks) when using these
constraints.
The following is an example of how to define I/O pin lock constraints:
• NET "RDat_P(15)" LOC = "G18";
• NET "RDat_P(14)" LOC = "B24";
• NET "RDat_P(13)" LOC = "F18";
• NET "RDat_P(12)" LOC = "E21";
• NET "RDat_P(11)" LOC = "A20";
• NET "RDat_P(10)" LOC = "D22";
To use these constraints, add the constraints and modify the pinout accordingly. If you use
an area group to define the placement of the Sink core, place the SPI-4.2 Lite pins (RCtl
and RDat) in the same clock region as the defined area group. This is especially needed if
regional clocking is used.
The user also has the same flexibility of placing RDClk using the above constraints type.
However, there are some general guidelines when using different clocking options.
If regional clocking is chosen, RDClk must be placed on a clock capable I/O pin that is in
the same clock region as the Lite Sink core logic.
To illustrate, in the example UCF file:
• INST "RDClk" LOC = "Bank5";
If global clocking is chosen, RDClk must be placed on a pin that is connected to a global
clock buffer. For instance, in the example UCF file: