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SPI-4.2 Lite v4.3 User Guide www.xilinx.com 107
UG181 June 27, 2008
Source Core Optional Constraints
R
• * INST "TSClk*" LOC = "Bank 9";
If global clocking is used, TSClk must be placed on a pin that is connected to a global clock
buffer.
Using the example UCF file:
• * INST "TSClk*" LOC = "Bank4";
IOB Register Packing
The following constraints are mandatory for the Source core. It ensures that the input
registers of the TStat signal are packed in the IOB. This guarantees that the timing
between the input pad and the register is met.
Source Core Optional Constraints
In addition to the required constraints, you can add the following optional constraints
based on your design requirements.
I/O Standards Constraints
You can define different I/O standards for several input and output pins. To change the
I/O standards for TSClk and TStat to LVTTL, add the following constraints in the
design:
• NET "TSClk" IOSTANDARD = LVTTL;
• NET "TStat" IOSTANDARD = LVTTL;
To change the I/O standards of the Source core input reference clock (SysClk) to LVPECL
33, add the following constraints in the design:
• NET "SysClk_P" IOSTANDARD = LVPECL_33;
To change the I/O standards of the Source core input reference clock (SysClk) to LVDS 25
with internal device termination or DCI, add the following constraints in the design:
• NET "SysClk_P" IOSTANDARD = LVDS_25_DCI;
• NET "SysClk_N" IOSTANDARD = LVDS_25_DCI;
To change the I/O standards of the source core input reference clock (SysClk) to LVDS 25
with internal differential termination, add the following constraints in the design:
• INST "<source_instance_name>/U0/pl4_lite_src_clk0/
sysclk_ibufg0" DIFF_TERM = TRUE;
Area Group Constraints
The area group constraints can be used to define a specific placement of the Source core.
These constraints are not required for Source cores that use global clocking distribution but
are recommended for Source cores that use regional clocking distribution.
Following is an example of an area group constraint for the Source core placed in one clock
region:
• * INST <src_instance_name>/* AREA_GROUP = AG_pl4_lite_src;
• * AREA_GROUP " AG_pl4_lite_src" RANGE = CLOCKREGION_X0Y3;