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SPI-4.2 Lite v4.3 User Guide www.xilinx.com 15
UG181 June 27, 2008
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Chapter 1
Introduction
The SPI-4.2 (PL4) Lite core implements and is functionally compliant to the OIF-SPI-4-02.1
System Packet Interface Phase 2 specification and supports both VHDL and Verilog design
environments.
This chapter introduces the SPI-4.2 Lite core and provides related information, including
recommended design experience, additional resources, technical support, and how to
submit feedback to Xilinx.
About the Core
The SPI-4.2 Lite core is a Xilinx CORE Generator IP core, included in the latest IP Update
on the Xilinx IP Center.
For detailed information about the core, see
www.xilinx.com/products/ipcenter/DO-DI-POSL4MC.htm
.
For information about system requirements, installation, and licensing options, see the
SPI-4.2 Lite Getting Started Guide.
Recommended Design Experience
Although the SPI-4.2 Lite core is a fully verified solution, the challenge associated with
implementing a complete design varies depending on the configuration and functionality
of the application. For best results, previous experience building high performance,
pipelined FPGA designs using Xilinx implementation software and user constraints files
(UCF) is recommended.
Contact your local Xilinx representative for a closer review and estimation for your specific
requirements.
Additional Core Resources
For detailed information and updates about the SPI-4.2 Lite core, see the following
documents, located on the SPI-4.2 product lounge page at:
www.xilinx.com/ipcenter/posphyl4/spi42_core.htm
• SPI-4.2 Lite Data Sheet
• SPI-4.2 Lite Release Notes
• SPI-4.2 Lite Getting Started Guide