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SPI-4.2 Lite v4.3 User Guide www.xilinx.com 117
UG181 June 27, 2008
Source Clocking Options
R
Figure 6-6: Source Clocking: Global Clocking for SysClk
Figure 6-7: Source Clocking: Global Clocking for TSClk
IOB DDR Flops
D Q
D Q
DCMReset_TDClk
Locked_TDClk
Denotes I/O on User Interface
TDat[15:0] & TCtl
IOB
SysClk0_GP
SysClk180_GP
Source Internal
Data & Control
Bus
D Q
SysClk0_GP
IOB
SysClk
CLK0
DCM
100 MHz
32
16
16
100 MHz
100 MHz
SysClk0_GP
100 MHz
100 MHz
100 MHz Path
200 MHz Path
SysClk180_GP
IBUFGDS
CLKIN
BUFG
TSClk_GP
IOB
EN
IOB
TStat[1:0]Internal Bus
TStat[1:0]
Q D
TSClk_GP
25 MHz
TSClk
BUFR
25 MHz
BUFIO