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136 www.xilinx.com SPI-4.2 Lite v4.3 User Guide
UG181 June 27, 2008
Appendix C: SPI-4.2 Lite Core Verification
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♦ SPI-4.2 bus traffic that caused the SPI-4.2 Lite sink FIFO to be constantly almost
full
♦ Backend data traffic that caused the SPI-4.2 Lite source FIFO to be constantly
almost full
♦ SPI-4.2 bus traffic that caused the sink FIFO to overflow
♦ Backend data traffic that caused the source FIFO to overflow
• Verification of invalid data
♦ SPI-4.2 bus traffic that contained incorrect DIP-4 values
♦ SPI-4.2 status traffic that contained incorrect DIP-2 values
♦ SPI-4.2 status traffic that indicated that the receiving end of the SPI-4.2 Lite source
block was out of frame
♦ SPI-4.2 bus traffic that violated SOP spacing and had incorrect control word
formats
♦ SPI-4.2 bus traffic that contained data bursts that were not preceded by payload
control words
♦ SPI-4.2 bus traffic that terminated on non-credit boundaries with no EOP.
♦ SPI-4.2 bus traffic that contained reserved control words
♦ Backend data traffic that contained no EOP with non-zero MODs.
The behavior of the core was fully verified for a range of core configurations. It was also
fully verified for the following range of clock frequencies.
♦ SPI-4.2 bus clock: 100 MHz to 275 MHz
♦ SrcFFClk and SnkFFClk: 50 MHz to 275 MHz
♦ SnkStatClk and SrcStatClk: 20 MHz to 100 MHz
♦ SrcCalClk and SnkCalClk: 20 MHz to 100 MHz