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SPI-4.2 Lite v4.3 User Guide www.xilinx.com 47
UG181 June 27, 2008
Source Status Options Screen
R
to normal. The valid range is the Almost Full Assert value to 508 and is also measured from
the full level.
Clocking
Clock Mode
The Sink core netlist will contain a complete clocking solution if Embedded Clocking is
selected. If User Clocking is selected, you must provide a clock generation method
external to the Source core. For more information, see “Sink Clocking Options,” page 111.
Clock Distribution
If User Clocking is selected for the Virtex-4 and Virtex-5 device architectures, the RDClk
clocking implementation can use either global or regional clock buffers. For more
information, see “Sink Clocking Options,” page 111.
Source Status Options Screen
This screen contains options for the static configuration parameters of the Source core. The
static configuration parameters below determine the behavior of the status interface.
Calendar
This describes the status pattern that the Source core expects on its status interface.
Iterations of Calendar Sequence Before DIP2
This is the value of static configuration signal SrcCalendar_M; it is the number of times
the Source core will expect the calendar sequence to repeat before seeing a DIP2 value and
framing on TStat. The valid range is 1 to 256.
Length of Calendar Sequence
This is the value of static configuration signal SrcCalendar_Len; it is the number of
entries in the calendar sequence. The valid range is 1 to 512.
Load Init File
If this option is selected, the Source core calendar block RAM will be initialized at startup
with a sequence loaded from a COE file.
Load Coefficients
This option lets you select the name of the COE file with calendar programming
information. For more information see “Calendar COE File Format,” page 50.
Show Coefficients
This option lets you view the contents of the loaded COE file.