Xilinx UG181 Welder User Manual


 
48 www.xilinx.com SPI-4.2 Lite v4.3 User Guide
UG181 June 27, 2008
Chapter 3: Generating the Core
R
Status Interface
Status FIFO Interface
This option selects whether the Source core netlist is generated with an addressable or
transparent user status interface. For more information, see the “Source Status and Flow
Control Signals,” page 85.
Status I/O
This option controls whether the Source core status I/O in the generated wrapper file uses
LVDS or LVTTL I/O.
Synchronization
These options select the default static configuration parameters for core synchronization.
Number of DIP2 Matches
This is the value of static configuration signal NumDIP2Matches; it is the number of
consecutive valid DIP2 words the Source core must observe on TStat before it goes in
frame, deasserts SrcOof, and begins to transmit data on TDat. The valid range is 1 to 15.
Number of DIP2 Errors
This is the value of static configuration signal NumDip2Errors; it is the number of
consecutive invalid DIP2 words the Source core must observe on TStat before going out-
of-frame. The valid range is 1 to 15.
Source Other Options Screen
This window contains options that affect data burst behavior, FIFO flag behavior, and
clocking implementation.
Bursting
This selects the static configuration parameters that determine Source core transmit
behavior.
Number of Data Cycles Before Training
This is the value of static configuration signal DataMaxT; it is the approximate number of
cycles of data the Source core will transmit on TDat between periodic training sequences.
The valid values are 0 and 16 to 65535. A value of 0 indicates that the core will not send
periodic training.
Number of Training Patterns During Training
This is the value of static configuration signal AlphaData; it is the number of training
patterns the Source core will transmit on TDat each time periodic training is sent. The valid
range is from 0 to 255. A value of 0 indicates that the core will not send periodic training.