Xilinx UG181 Welder User Manual


 
Schedule of Figures
Chapter 2: Core Architecture
Figure 2-1: SPI-4.2 Lite Core in a Typical Link Layer Application. . . . . . . . . . . . . . . . . . . 18
Figure 2-2: Sink Core Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 2-3: Source Core Block Diagram and I/O Interface Signals . . . . . . . . . . . . . . . . . . 31
Chapter 3: Generating the Core
Figure 3-1: SPI-4.2 Lite Sink and Source Main Customization Screen . . . . . . . . . . . . . . . 44
Chapter 4: Designing with the Core
Figure 4-1: SPI-4.2 Interface to the 64-Bit User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 4-2: Sink Data Path - Short Packet Transfers with Minimum SOP Spacing
Enforced. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 4-3: Sink Training Valid Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 4-4: Sink FIFO Almost Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 4-5: Sink FIFO Empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 4-6: Status FIFO Calendar and Status Memory Block Diagram. . . . . . . . . . . . . . . 62
Figure 4-7: Sink Calendar Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 4-8: Typical Flow Control Implementation for 4-Channel System . . . . . . . . . . . . 64
Figure 4-9: Sink Status FIFO Interface Example 1: 10-channel Configuration. . . . . . . . . 65
Figure 4-10: Sink Status FIFO Interface Example: 64-channel Configuration . . . . . . . . . 66
Figure 4-11: Sink Status Path - User Interface to SPI-4.2 Interface. . . . . . . . . . . . . . . . . . . 67
Figure 4-12: FIFO Almost Full Mode “00”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 4-13: FIFO Almost Full Mode “01”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 4-14: FIFO Almost Full Mode “10” or “11” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 4-15: Sink Startup Sequence State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 4-16: Short Packet Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 4-17: Sequential Payload Control Word Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 4-18: Example of Error Flag SnkFFDIP4Err . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 4-19: Example of Error Flag SnkFFDIP4Err and SnkFFPayloadDIP4 . . . . . . . . . . 75
Figure 4-20: Example of Error Flag SnkFFPayloadErr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 4-21: Source Data Path: User Interface to SPI-4.2 Interface. . . . . . . . . . . . . . . . . . . 77
Figure 4-22: Source Data Path - Minimum SOP Spacing Enforced . . . . . . . . . . . . . . . . . . 78
Figure 4-23: Source Data Path - Short Packet Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 4-24: Source FIFO Almost-full Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 4-25: Source FIFO Overflow Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 4-26: Writing to the Source FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 4-27: Typical User Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 4-28: Source Calendar Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 4-29: Addressable Status FIFO Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88