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SPI-4.2 Lite v4.3 User Guide www.xilinx.com 71
UG181 June 27, 2008
Sink Core
R
Figure 4-15 shows a state machine diagram illustrating the Sink core startup sequence and
error condition processing.
Reset
The Sink core remains in the Reset state until the following conditions are true:
• Reset_n is deasserted
• SnkEn is asserted
In this state, the Sink core transmits framing patterns (11) on RStat[1:0]. The core is Out
of Frame in this state.
Hunt
The core remains in the hunt state until a set number of consecutive training patterns are
received as defined by the parameter NumTrainSequences
In this state, the Sink core transmits framing patterns (11) on RStat[1:0]. The core is Out
of Frame in this state.
Sync Wait
In the Sync Wait state, the Sink core has completed the start-up sequence and is waiting to
receive the first valid SOP to data transition on RDat.
The Sink core will remain in this state until the following conditions are true:
• SnkFifoReset_n is deasserted
• The first valid SOP-to-data transition is received on RDat
In this state, the Sink core continuously checks DIP-4 parity, and sends FIFO Channel
status on RStat. The core is In Frame in this state.
Figure 4-15: Sink Startup Sequence State Machine
RESET HUNT
SYNC
WAIT
SYNC
DATA
SYNC
TRAIN
FIFO Reset
Asserted
Reset De-asserted;
Sink Enabled
Consecutive DIP4
Errors Received;
Almost Full and
FifoAFMode = "00"
Reset Asserted;
Sink Disabled
Consecutive Valid
Training Sequences
Received
Valid SOP to Data
Transition Detected;
FIFO Reset De-asserted
Training Pattern
Detected
Data Transition Detected