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SPI-4.2 Lite v4.3 User Guide www.xilinx.com 121
UG181 June 27, 2008
Multiple Core Implementations
R
);
When instantiating the cores, there are several synthesis attributes that must be included.
The cores need to be defined as black boxes for the synthesis tool, and automatic insertion
of IBUF or OBUF signals for the SPI-4.2 Lite interface signals must be disabled.
For example, in VHDL and Synplicity:
Attribute syn_black_box: boolean ;
Attribute black_box_pad_pin: string ;
Attribute syn_black_box of pl4_lite_snk_top1 : component is true;
Attribute black_box_pad_pin of pl4_lite_snk_top1: component is
“RDClk_P, RDClk_N, RDat_P(15:0), RDat_N(15:0), RCtl_P, RCtl_N” ;
Attribute syn_black_box of pl4_lite_snk_top2 : component is true;
Attribute black_box_pad_pin of pl4_lite_snk_top2 : component is
“RDClk_P, RDClk_N, RDat_P(15:0), RDat_N(15:0), RCtl_P, RCtl_N”;
Attribute syn_black_box of pl4_lite_src_top1 : component is true ;
Attribute black_box_pad_pin of pl4_lite_src_top1: component is
“SysClk_P, SysClk_N, TDClk_P, TDClk_N, TDat_P(15:0), TDat_N(15),
TCtl_P, TCtl_N” ;
Attribute syn_black_box of pl4_lite_src_top2 : component is true ;
Attribute black_blox_pad_pin of pl4_lite_src_top2 : component is
“SysClk_P, SysClk_N, TDClk_P, TDClk_N, TDat_P(15:0), TDat_N(15:0),
TCtl_P, TCtl_N” ;
Examples of the attributes are available in the delivered example wrapper files:
<proj>/implement/<vhdl/verilog>/*.v<vhd>
Generating the Cores
For each core that will be instantiated, unique netlists (with unique component names)
must be generated using the Xilinx CORE Generator. Each NGC file must also be renamed
to match the component names in the top-level file.
For example:
pl4_
lite_snk_top1.ngc
pl4_
lite_snk_top2.ngc
pl4_
lite_src_top1.ngc
pl4_
lite_src_top2.ngc
Creating Top-Level UCF File
When instantiating multiple cores, each core is generated separately by the CORE
Generator system and includes a separate top-level UCF file. The user must merge the top-
level UCF files generated for each core to produce a single UCF file with all required
constraints.