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SPI-4.2 Lite v4.3 User Guide www.xilinx.com 83
UG181 June 27, 2008
Source Core
R
The control signal TrainingRequest is used to request that training patterns be sent out
of the Source SPI-4.2 interface. When this signal is asserted, data transmission is halted on
the next burst boundary and training patterns are transmitted on the SPI-4.2 Interface. For
more information on the behavior of TrainingRequest, see “Transmitting Training
Patterns”.
The control signal IdleRequest signals that idle control words are to be sent on the SPI-
4.2 bus. This request overrides payload data transfers, but not training sequence requests.
When this signal is asserted, the data transmission is halted on the next burst boundary
and idle cycles are transmitted on the SPI-4.2 Interface. Idle cycles continue to be
transmitted until the signal is deasserted. For more information, see “Transmitting Idle
Cycles”.
The control signal SrcTriStateEn allows you to set the IOB drivers to high impedance
for Source core output signals TDClk, TDat[15:0], and TCtl. The Source core has the
default setting for this signal as outputs not to be tri-stated (SrcTriStateEn=0).
The control signal SrcOofOverride removes the requirement that the Source core must
receive consecutive valid DIP2 values on TStat. This signal forces the Source core to go in-
frame, and begin transmitting data on the SPI-4.2 interface. This signal is intended for
system testing and debugging.
The control signals SrcFifoReset_n and Reset_n provide reset capability to you:
• SrcFifoReset_n is used to clear the FIFO (and the associated data path logic) while
remaining in-frame. When SrcFifoReset_n is deasserted, the Source core will send
idle cycles until you write data into the FIFO.
• Reset_n is used to restart the entire Source core, and causes the interface to go out-
of-frame. When Reset_n is deasserted, the Source core will initiate the
synchronization startup sequence.
Source FIFO Interface Signals
The Source FIFO Interface signals allow you to write data to the FIFO for transmission to
the SPI-4.2 Interface. The description of each signal is summarized in Table 2-12. The
Source FIFO Interface signals are synchronous to SrcFFClk, and the effective FIFO depth
is 510 words. A FIFO word is 1/2 credit wide for a 64-bit interface, and 1/4 credit wide for
a 32-bit interface.
The SPI-4.2 Source core offers 64- and 32-bit FIFO Interface options for writing data into the
FIFO. Waveforms illustrating handshaking and FIFO status signals are shown in
Figure 4-24, Figure 4-25, and Figure 4-26. The Source core also supports insertion of DIP-4
errors on a per-packet basis for system diagnostics. For more information, see “Insertion of
DIP-4 Errors,” page 85.
Source FIFO Almost Full
Figure 4-24 shows the Almost Full response of the Source FIFO. The behavior of the Source
Almost Full flag (SrcAlmostFull_n) is dependent on the static configuration signals
SrcAFThresAssert and SrcAFThresNegate. When the SrcAlmostFull_n flag is
asserted, SrcAFThresAssert specifies the number of available empty FIFO locations.
For a 64-bit user interface, each FIFO location can contain up to 1/2 credit (8 bytes) worth
of data from a single packet. For a 32-bit user interface, each FIFO location can contain up
to 1/4 credit (4 bytes) worth of data from a single packet. SrcAFThresNegate specifies
when the SrcAlmostFull_n flag is deasserted.