Xilinx UG181 Welder User Manual


 
110 www.xilinx.com SPI-4.2 Lite v4.3 User Guide
UG181 June 27, 2008
Chapter 5: Constraining the Core
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INST "TCtl*" LOC = "Bank7"; # 1 LVDS I/O pair
INST "TDat*" LOC = "Bank7"; # 16 LVDS I/O pair
Specify pin placement for "TSClk" I/O. See “Placement Constraints,” page 105. For
example:
INST "TSClk" LOC = "Bank3";
Specify an area group constraint if regional clocking is used. In the example UCF file, area
group "AG_pl4_lite_ src" is defined to be one clock region on the same side of the device.
AREA_GROUP "AG_pl4_lite_src" RANGE = CLOCKREGION_X0Y0;