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46 www.xilinx.com SPI-4.2 Lite v4.3 User Guide
UG181 June 27, 2008
Chapter 3: Generating the Core
R
Rate
This is the value of static configuration signal RSClkDiv; it selects the frequency of RSClk
with respect to RDClk.
Alignment
This is the value of static configuration signal RSClkPhase; it determines whether RStat
transitions on the rising or falling edge of RSClk.
Status I/O
This controls whether RStat and RSClk I/O in the generated wrapper file use LVDS or
LVTTL I/O.
Sink Other Options Screen
This window contains options that affect the FIFO flags, clocking implementation, status
channel behavior, and I/O type.
Synchronization
These options select the default static configuration parameters for core synchronization.
Number of Training Sequences
This is the value of static configuration signal NumTrainSequences; it is the number of
training sequences the Sink core must receive on RDat before going in-frame and transiting
from framing to status on RStat. The valid range is 1 to 15.
Number of DIP4 Errors
This is the value of static configuration signal NumDIP4Errors; it is the number of
consecutive control words with invalid DIP4 values the Sink core must receive on RDat
before going out-of-frame and sending framing on RStat. The valid range is 1 to 15.
FIFO Threshold
These options select the default static configuration parameters for Sink core FIFO
Threshold behavior.
Almost Full Assert
This is the value of static configuration signal SnkAFThresAssert; it is the internal FIFO
level at which the Sink core will assert SnkFFAlmostFull_n and take the specified flow
control action. The valid range is 1–508 and is measured from the full level. For example, if
the value chosen is 10, SnkFFAlmostFull_n will be asserted when there are 10 FIFO
locations empty.
Almost Full Negate
This is the value of static configuration signal SnkAFThresNegate; it is the internal FIFO
level at which the Sink core will deassert SnkFFAlmostFull_n and return RStat behavior