Xilinx UG181 Welder User Manual


 
SPI-4.2 Lite v4.3 User Guide www.xilinx.com 61
UG181 June 27, 2008
Sink Core
R
operations occurring on the sink user interface. Configure the SnkAFThresAssert value
according to your specific system requirements.
See “FifoAFMode and Sink Almost Full,” page 67 for a description of the behavior of Sink
FIFO interface when the Sink Almost Full flag is asserted.
Sink Overflow
The assertion of Sink Overflow flag (SnkOverflow_n) indicates that there is a write
operation attempted on the FIFO when there are no empty FIFO locations available. This
results in data loss since no more data will be written into the FIFO until it is not in a full
state. When the overflow condition occurs, it is recommended that you reset the FIFO since
data corruption has occurred. To avoid the overflow condition, you should use the Sink
Almost Full flag to gauge the readiness of the sink core to receive data (see “FifoAFMode
and Sink Almost Full,” page 67.)
Sink Status and Flow Control Signals
The Sink Status FIFO interface enables you to send flow control data on the SPI-4.2
Interface. The channel order and frequency that the status is sent is user-programmed in a
calendar. A two-bit register is provided for each location in the calendar to store the
channel status information (hungry=01, starving=00, satisfied=10). Figure 4-6 illustrates
how the calendar information is retrieved to determine the order and frequency that a
particular channel’s FIFO Status information is transmitted on RStat. A detailed
description of the calendar interface and the Status FIFO interface is provided in the
following section. A summary of the Sink Status Path signals and their definitions is
provided in Table 2-4 and Table 2-5.