Filter
Top Products
SPI-4.2 Lite v4.3 User Guide www.xilinx.com 99
UG181 June 27, 2008
R
Chapter 5
Constraining the Core
This chapter describes the timing and placement constraints required by the SPI-4.2 Lite
core to meet the performance requirements, including a set of optional constraints. These
constraints are provided in an example user constraints file (UCF).
In this chapter, <snk_instance_name> and <src_instance_name> are used to
indicate the instance name used to instantiate the Sink and Source cores in HDL
respectively. Depending on where the cores are instantiated in the user design hierarchy,
<*instance_name> will change to include the design hierarchy.
For example, in the example UCF file, the cores are instantiated in a top-level wrapper file
as “<component_name>_pl4_lite_snk_top0” and
“<component_name>_pl4_lite_src_top_master_addr0.” Therefore, the
<snk_instance_name> used for the Sink core is
“<component_name>_pl4_lite_snk_top0” and the <src_instance_name> used
for the Source core is “<component_name>_pl4_lite_src_top_master_addr0”. In
this context, <component_name> is the name given by the user in the CORE Generator
SPI-4.2 Lite GUI.
Overview
The SPI-4.2 Lite core provides flexibility to the user to drive constraints with user-specific
design requirements. The large number of possible core implementations makes it
impossible to include constraints for all of them. Even if such constraints were generated,
they would tend to be less than optimal for any particular FPGA design. In many cases,
only the timing constraints are required to ensure correct implementation of the core. Any
configuration that achieves static timing closure (for example, meets the timing constraints
of the operating clock frequency) is valid and will operate correctly.
The following sections describe how each set of constraints provided in the example UCF
file interacts with the implementation tool flow. In many cases, the placement constraints
are not required. However, when used, they must be appropriately modified for the
chosen device and consistent with other constraints. For example, I/O bank locations and
Sink and Source clock region constraints need to be compatible if used together. For more
information about the definition and use of a UCF file or specific constraints, see the Xilinx
Libraries Guide and/or Development System Reference Guide.
Sink Core Required Constraints
Timing Constraints
Timing constraints are crucial for proper operation. The following constraints are provided
with the SPI-4.2 Lite core, but can be modified to meet individual system requirements. In