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SPI-4.2 Lite v4.3 User Guide www.xilinx.com 41
UG181 June 27, 2008
Source Core Interfaces
R
DCMLost_TDClk Output N/A Indicates TDClk input has stopped (status
bit one of TDClk DCM)
SrcClksRdy Output N/A Indicates all Source core clocks are ready
for use.
Table 2-18: Source Core Clocks: Slave Configuration
Clock Pins Direction Description Max Freq.
SysClk0_GBSLV Input
(user interface)
SysClk0: This clock is
used to clock the internal
source core logic.
Virtex-5: 275 MHz
Virtex-4: 190 MHz
Virtex-II Pro: 160 MHz
Virtex-II: 160 MHz
Spartan-3: 115 MHz
Spartan-3E: 90 MHz
Spartan-3A/3AN/3A DSP:
105 MHz
SysClk180_GBSL
V
Input
(user interface)
SysClk180: This clock is
the inverted equivalent of
SysClk0_GBSLV. It is used
to clock the internal
Source core logic.
Virtex-5: 275 MHz
Virtex-4: 190 MHz
Virtex-II Pro: 160 MHz
Virtex-II: 160 MHz
Spartan-3: 115 MHz
Spartan-3E: 90 MHz
Spartan-3A/3AN/3A DSP:
105 MHz
TSClk_GBSLV Input
(user interface)
TSClk: This clock is one-
fourth the frequency of
TDClk.
Virtex-5: 69 MHz
Virtex-4: 47.5 MHz
Virtex-II Pro: 40 MHz
Virtex-II: 40 MHz
Spartan-3: 28.75 MHz
Spartan-3E: 22.5 MHz
Spartan-3A/3AN/3A DSP:
105 MHz
Table 2-17: Source Core Clock Status Signals: Master Configuration (Continued)
Signal Name Direction
Clock
Domain
Description