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SPI-4.2 Lite v4.3 User Guide www.xilinx.com 129
UG181 June 27, 2008
Xilinx Tool Flow
R
Static Timing Analysis
To evaluate timing closure on a design and create a timing report file (TWR) derived from
static timing analysis of the physical design file (NCD), the trce command must be
executed. The analysis is typically based on constraints included in the optional physical
constraints file (PCF). An example of the trce command is provided below:
trce -e 10 routed.ncd mapped.pcf -o routed.twr
The trce command outputs a routed.twr file, which performs timing analysis of the
placed and routed design based on the user constraints.
Timing Simulation
After the user design is functionally correct and meets all timing constraints, it is
recommended the user perform back-annotated timing simulation to verify that the entire
user design will function correctly before the user tests their design in hardware. The
netgen command is used to generate a post-par simulation model, which includes all
timing information. An example of the netgen command is provided below:
netgen -sim -ofmt <vhdl | verilog> routed.ncd
The netgen command outputs routed.v[hd] and routed.sdf files, which allow the user to
run timing simulation.
Generating a Bitstream
To create the configuration (BIT) file based on the contents of a physical implementation
file (NCD), the bitgen command must be executed. The BIT file defines the behavior of the
programmed FPGA. An example of the bitgen command is provided below:
bitgen -w routed.ncd
Note the user should take care in setting the required bitgen options, including selection of
the startup clock. See the Development System Reference Guide for details.