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22 www.xilinx.com SPI-4.2 Lite v4.3 User Guide
UG181 June 27, 2008
Chapter 2: Core Architecture
R
Sink User Interface
The Sink User Interface includes all signals other than those on the SPI-4.2 Interface. The
high-performance logic on the Sink back-end enables the user interface to run at higher
frequencies than the SPI-4.2 Interface. This is sometimes required if a large percentage of
the traffic consists of small packets.
The User Interface is subdivided into five smaller interfaces. Each of these interfaces are
presented in detail below:
• Control and Status Interface: The signals of this interface apply to the operation of
the Sink core.
• FIFO Interface: The signals of this interface allow you to access data received on the
SPI-4.2 Interface.
• Status and Flow Control Interface: The signals of this interface send flow control
information on the SPI-4.2 Interface.
• Static Configuration Interface: The signals of this interface allow you to configure the
core.
• Clocking Interface: The signals of this interface report the status of the clocks and
include the general purpose clocks.
Sink Control and Status Interface
The Sink core control and status signals either control the operation of the entire Sink core
or provide status information that is not associated with a particular channel (port) or
packet. Table 2-2 defines the Sink control and status signals.
Table 2-2: Sink Control and Status Signals
Name Direction
Clock
Domain
Description
Reset_n Input n/a Reset: Active Low signal that asynchronously initializes internal flip-flops,
registers, and counters. When Reset_n is asserted, the Sink core will go out
of frame and the entire data path is cleared (including the FIFO). The Sink
core will also assert SnkOof, and deassert SnkBusErr and SnkTrainValid.
When Reset_n is asserted, the Sink core will transmit framing "11" on RStat
and continue to drive RSClk.
Following the deassertion of Reset_n, the sink calendar should be
programmed if the calendar is initialized in-circuit.
SnkFifoReset_n Input SnkFFClk Sink FIFO Reset: Active low signal enables you to reset the Sink FIFO and
the associated data path logic. This enables the FIFO to be cleared while
remaining in frame.
Coming out of SnkFifoReset_n, the Sink core will discard all data on the SPI-
4.2 interface until a valid SOP control word is received.
SnkEn Input SnkStatClk Sink Enable: Active high signal that enables the Sink core. When SnkEn is
deasserted, the Sink core will go out of frame and will not store any
additional data in the FIFO. The current contents of the FIFO remain intact.
The Sink core will also assert SnkOof, and deassert SnkBusErr and
SnkTrainValid. When SnkEn is deasserted, the Sink core will transmit
framing "11" on RStat and continue to drive RSClk.