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SPI-4.2 Lite v4.3 User Guide www.xilinx.com 127
UG181 June 27, 2008
Synthesis
R
Before attempting timing simulation, follow the steps below to ensure that the simulator
environment is properly configured.
1. Compile the Xilinx SimPrim libraries (if not already compiled). For details, see Xilinx
Answer Record 15338.
2. Run the design through the Xilinx tool flow. An implement script is provided with the
example design. The user may use this script as an example for creating their
environment. For details about the implementation script, see the SPI-4.2 Lite Getting
Started Guide.
3. Compile the post-par simulation model. An example timing simulation script is
provided with the example design, and may be used as an example for creating the
user test environment. For details about the timing simulation script, see the SPI-4.2
Lite Getting Started Guide.
Synthesis
Synthesis of Example Design
Synthesis of the example design is supported by XST and Synplify. While other synthesis
tools may be used to synthesize the example design, they have not been tested and
functionality can not guaranteed. For detailed use of the example design, see the SPI-4.2
Lite Getting Started Guide.
XST
Before synthesizing with XST, be sure that the Xilinx environment is properly configured
for use. A sample synthesis script is provided in the implement directory and can be used
as an example for synthesizing the user design.
1. Create an XST project file or open the Xilinx ISE™ GUI.
2. Add the necessary user source files to the project file or ISE GUI. If creating a project
file, also add the unisim_comp.v[hd] file located in the <Xilinx Install Path>/[vhdl |
verilog]/src/ise/ directory. This file is included automatically when using
the ISE GUI.
3. Synthesize the user application.
• If using the Project Navigator ISE environment, double-click Synthesize-XST in
the Processes for Source window. Set the HDL language to VHDL or Verilog, the
results directory and the part being used.
• If the command line mode is being used, at the prompt, start an XST shell session
by typing xst at the prompt and hitting enter. Synthesize the design by calling the
XST run command to process the files in the project file.
• For additional options that can be set to further customize synthesis of the user
design, see the XST section of the Xilinx development tools manual, located at
www.xilinx.com/documentation
.
Synplify
Before synthesizing with Synplify, make sure that the Synplify environment is properly
configured for use. A sample synthesis script is provided in the implement directory,
which can be used as an example for the synthesizing the user design.
1. Create a Synplify project file.