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SPI-4.2 Lite v4.3 User Guide www.xilinx.com 49
UG181 June 27, 2008
Source Other Options Screen
R
Burst Size in Credits
This is the value of static configuration signal SrcBurstLen; it is the maximum burst length
in credits. The valid range is from 1 to 63.
Burst Mode
This is the value of static configuration signal SrcBurstMode. It specifies how the Source
core transmits data. Complete Bursts Only causes the core to send only data bursts that
are of Burst Size (as defined above) or terminated by an EOP. Segmentation of Bursts at
Credit Boundary causes the core to send data bursts that terminate at any credit boundary
or with an EOP. See“Source Burst Mode,” page 93.
FIFO Threshold
This option lets you select the default static configuration parameters for Source core FIFO
Threshold behavior.
Almost Full Assert
This is the value of static configuration signal SrcAFThresAssert; it is the internal FIFO
level at which the Source core will assert SrcFFAlmostFull_n. When the burst mode is
selected to be complete burst only, the valid range of SrcAFThresAssert is from
SrcBurstLen to 508, otherwise the valid range is from 6 to 508. The Almost Full Assert value
is measured from the full level. For example, if the value chosen is 40,
SrcFFAlmostFull_n will be asserted when there are 40 FIFO locations empty.
Almost Full Negate
This is the value of static configuration signal SrcAFThresNegate; it is the internal FIFO
level at which the Source core will deassert SrcFFAlmostFull_n. The valid range is the
Almost Full Assert value to 508 and is also measured from the full level.
Clocking
Clock Mode
The Source core netlist will contain a complete clocking solution if Master Clocking is
selected. If Slave Clocking is selected, you must provide a clock generation method
external to the Source core. For more information, see “Source Clocking Options,” page
115.
SysClk Distribution
For Virtex-4 and Virtex-5 FPGA designs, the SysClk internal clocking implementation uses
either the global clock buffers or the regional clock buffers. For more information, see
“Source Clocking Options,” page 115.
TSClk Distribution
For Virtex-4 FPGA designs, the TSClk internal clocking implementation uses either the
global clock buffers or the regional clock buffers. For more information, see “Source
Clocking Options,” page 115.