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32 www.xilinx.com SPI-4.2 Lite v4.3 User Guide
UG181 June 27, 2008
Chapter 2: Core Architecture
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In addition to transmitting 16-bit data words, the SPI-4.2 interface also receives flow
control data at 1/4 rate of its data interface. The 2-bit status received can be presented to
you in 2 interfaces: transparent and addressable.
Table 2-10 defines the Source SPI-4.2 interface signals.
Source User Interface
The Source User Interface includes all signals other than those on the SPI-4.2 interface. The
high performance logic on the Source back-end enables the user interface to run at higher
frequencies than the SPI-4.2 interface. This is sometimes required if a large percentage of
the traffic consists of small packets.
The Source User Interface is subdivided into 5 smaller interfaces. Each of these signal types
are presented in detail below:
• Control and Status Interface. The signals of this interface apply to the operation of
the Sink core.
• FIFO Interface. The signals of this interface allow you to access data received on the
SPI-4.2 Interface.
• Status and Flow Control Interface. The signals of this interface send flow control
information on the SPI-4.2 Interface.
• Static Configuration Interface.The signals of this interface allow you to configure the
core.
• Clocking Interface. The signals of this interface report the status of the clocks and
include the general purpose clocks.
Table 2-10: Source SPI-4.2 Interface Signals
Name Direction
Clock
Domain
Description
TDClk_P
TDClk_N
Output n/a SPI-4.2 Transmit Data Clock (LVDS): Source
synchronous clock transmitted with TDat. The
rising and falling edges of this clock (DDR) are
used to clock TDat and TCtl.
TDat_P[15:0]
TDat_N[15:0]
Output TDClk SPI-4.2 Transmit Data Bus (LVDS): The 16-bit data
bus is used to transmit SPI-4.2 data and control
information.
TCtl_P
TCtl_N
Output TDClk SPI-4.2 Transmit Control (LVDS): SPI-4.2 Interface
signal that defines whether data or control
information is present on the TDat bus. When TCtl
is Low, data is present on TDat. When TCtl is High,
control information is present on TDat.
TSClk
Input n/a SPI-4.2 Transmit Status Clock: Source
synchronous clock that is received by the Source
core with TStat at 1/4 rate (or 1/8 rate) of TDClk.
You can select this signal to be transmitted as
LVTTL or LVDS.
TStat[1:0] Input
TSClk
SPI-4.2 Transmit FIFO Status: FlFO-Status-
Channel flow control interface. You can select this
bus to be transmitted as LVTTL or LVDS.