Filter
Top Products
SPI-4.2 Lite v4.3 User Guide www.xilinx.com 103
UG181 June 27, 2008
Sink Core Optional Constraints
R
• INST "RDClk*" LOC = "Bank3";
IOB Register Packing
The following constraints are mandatory for the Sink core. It ensures that the output
register 3 of the RStat and RSClk signals are packed in the IOB. This guarantees that the
timing between the output pad and the register is met.
• INST "<snk_instance_name>/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/
rstat1_ff" IOB=TRUE;
• INST "<snk_instance_name>/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/
rstat0_ff" IOB=TRUE;
• INST "<snk_instance_name>/U0/pl4_lite_snk_core0/pl4_lite_snk_cal0/
r sclk_ff" IOB=TRUE;
Sink Core Optional Constraints
In addition to the required constraints, the following constraints can be used based on your
design requirements.
IDelayCtrl
The following constraint defines where to place the IDelayCtrl. It must be placed in the
I/O banks where the SPI-4.2 Lite I/Os are placed.
• INST "<snk_instance_name>/rdclk_idelctl” = IDELAYCTRL_X0Y4;
I/O Standards Constraints
Different I/O standards for several input and output pins can be defined. To change the
I/O standards for SnkIdelayRefClk (regional clocking only), RSClk, and RStat to
LVTTL, add the following constraints in the design:
• NET "SnkIdelayRefClk" IOSTANDARD = LVTTL;
• NET "RSClk" IOSTANDARD = LVTTL;
• NET "RStat" IOSTANDARD = LVTTL;
To change the I/O standards of the SPI-4.2 Lite data bus, control bit, and clock inputs to
LVDS 25 with internal device termination or DCI, add the following constraints in the
design:
• INST "RDat_P(*)" IOSTANDARD = LVDS_25_DCI;
• INST "RDat_N(*)" IOSTANDARD = LVDS_25_DCI;
• INST "RCtl_P" IOSTANDARD = LVDS_25_DCI;
• INST "RCtl_N" IOSTANDARD = LVDS_25_DCI;
• INST "RDClk_P" IOSTANDARD = LVDS_25_DCI;
• INST "RDClk_N" IOSTANDARD = LVDS_25_DCI;
To change the I/O standards of the SPI-4.2 Lite data bus, control bit, and clock inputs to
LVDS 25 with internal differential termination, add the following constraints in the design:
• INST "<sink_instance_name>/U0/pl4_lite_snk_clk0/rdclk_ibufg0"
DIFF_TERM = TRUE;