Filter
Top Products
114 www.xilinx.com SPI-4.2 Lite v4.3 User Guide
UG181 June 27, 2008
Chapter 6: Special Design Considerations
R
.
Regional Clocking
This implementation uses the regional clock buffer resources BUFIO and BUFR to generate
a full-rate clock (RClk0_USER) and inverted full-rate clock (RDClk180_USER). The user
clocking module also contains IDELAYCTRL and IDELAY modules for phase-shifting the
clock outputs. This is a requirement for static alignment of the clock to the data eye.
Regional clocking distribution in the Sink core requires a 200 MHz reference clock to clock
the IDELAYCTRL module. This guarantees predictable tap delays when shifting the clocks
with the IDELAY module. This extra clock should be considered when implementing
regional clocking in the Sink core. The regional clocking configuration is illustrated in
Figure 6-4. Note that the inverter used to generate the RDClk180_USER clock will be
absorbed into the DDR flops.
Figure 6-3: Sink User Clocking: Global Clocking
RDClk0_USER
IOB
RDClk
DCMReset_RDClk
Locked_RDClk
Denotes I/O on User Interface
RDat[15:0] & RCtl
IOB
Q D
Q D
RDClk0_GP
RDClk180_GP
IOB DDR Flops
CLK2X
RDClk0_GP
Q D
Sink Internal
Data & Control
Bus
RDClk0_GP
D Q
EN
Enable at ¼ (or 1/8) PL4 Rx data rate
IOB
RStat[1:0] & RSClkInternal Bus
RStat[1:0] & RSClk
CLK0
CLK180
DCM
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
25 MHz
32
16
16
200 MHz Path
RDClk180_USER
IBUFGDSBUFG
100 MHz Path