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82 www.xilinx.com SPI-4.2 Lite v4.3 User Guide
UG181 June 27, 2008
Chapter 4: Designing with the Core
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Transmitting Idle Cycles
Idle cycles are sent on the SPI-4.2 Interface only when there is no data in the FIFO. The core
will also insert idle cycles when the control signal IdleRequest (see Table 2-11) is
asserted. When this signal is asserted, the transmission of data is halted on the next burst
boundary and idle cycles are forced onto the SPI-4.2 Interface. The insertion of training
patterns always takes precedence over the transmission of idle cycles.
Inserting DIP4 Errors
For system diagnostics, one can force DIP4 errors to be inserted with a specific packet. This
is supported by using the SrcFFErr signal. When SrcFFErr is asserted and SrcFFEOP is
deasserted, it signals the core to terminate the current packet with an EOP and to force the
insertion of an erroneous DIP4 value. See “Inserting DIP4 Errors,” page 82.
Source User Interface
The Source User Interface includes all the signals to the core that are not found on the SPI-
4.2 Interface (See “Source SPI-4.2 Interface”). This user interface can operate up to 190 MHz
in Virtex-4 devices and 275 MHz in Virtex-5 devices with a 64- or 32-bit data interface.
The user interface has three types of signals:
• Control and Status Signals. These signals apply to the operation of the Source core
• FIFO Interface Signals. These signals allow you to write data to the FIFO to be
transmitted on the SPI-4.2 Interface
• Status and Flow Control Signals. These signals are used to receive flow control
information from the SPI-4.2 Interface
Source Control and Status Signals
The Source core control and status signals control the operation of the entire Source core
and provide status information that is not associated with a specific channel (port) or
packet. Descriptions for these signals can be found in Table 2-11, page 33.
The Source core is reset asynchronously by the signal Reset_n, and there are three global
status signals:
• Source Out-of-Frame (SrcOof) is asserted whenever the core has lost
synchronization with the SPI-4.2 status bus (TStat).
• Source DIP2 Error (SrcDIP2Err) is asserted when a DIP2 error is detected on the
SPI-4.2 status bus.
• Source Status Frame Error (SrcStatFrameErr) is asserted when a non-”11” frame
word is detected on the SPI-4.2 bus.
• Source Pattern Error (SrcPatternErr) is asserted when an illegal data pattern is
written into the Source FIFO. There are two conditions that trigger this error signal:
♦ The address was changed on a non-credit boundary, without an EOP. In this
case, the remainder of that packet will be terminated with an EOP Abort, and sent
out the SPI-4.2 bus.
♦ The SrcFFMod signal is non-zero without an EOP. In this case an EOP abort will
not be asserted. When this occurs, the Source core will ignore the SrcFFMod
value and send the data word with MOD set to zero.