Output
Switch
@
The output switch is U2 which is a quad ECL NOR gate. For frequency spans greater than
n x 100 kHz, but less than or equal to n
x
5 MHz, the switch input to R3 is TTL low.
U2B
and U2C are on while U2D is off. For all other spans, the opposite states exist. This has the
effect of switching either the output of U3 divider or
Jl
to the
20/30
loop output J2.
Divide
by
IO
@
Q3 is a common-emitter amplifier which drives U3 through a high-pass filter. U3 is an ECL
divide by 10 counter which generates the necessary 19.99 MHz to 30 MHz from the
PLLl
vco output.
2
AlOAl