Cisco Systems A9014CFD Router User Manual


 
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Cisco ASR 901 Series Aggregation Services Router Software Configuration Guide
OL-23826-09
Chapter 22 Configuring Clocking
Configuring Network Clock for Cisco ASR 901 Router
Understanding SSM and ESMC
Network Clocking uses these mechanisms to exchange the quality level of the clock between the network
elements:
Synchronization Status Message, page 22-7
Ethernet Synchronization Messaging Channel, page 22-7
Synchronization Status Message
Network elements use Synchronization Status Messages (SSM) to inform the neighboring elements
about the Quality Level (QL) of the clock. The non-ethernet interfaces such as optical interfaces and
SONET/T1/E1 SPA framers use SSM. The key benefits of the SSM functionality are:
Prevents timing loops.
Provides fast recovery when a part of the network fails.
Ensures that a node derives timing from the most reliable clock source.
Ethernet Synchronization Messaging Channel
In order to maintain a logical communication channel in synchronous network connections, ethernet
relies on a channel called Ethernet Synchronization Messaging Channel (ESMC) based on IEEE 802.3
Organization Specific Slow Protocol standards. ESMC relays the SSM code that represents the quality
level of the Ethernet Equipment Clock (EEC) in a physical layer.
The ESMC packets are received only for those ports configured as clock sources and transmitted on all
the SyncE interfaces in the system. The received packets are processed by the clock selection algorithm
and are used to select the best clock. The Tx frame is generated based on the QL value of the selected
clock source and sent to all the enabled SyncE ports.
Clock Selection Algorithm
Clock selection algorithm selects the best available synchronization source from the nominated sources.
The clock selection algorithm has a non-revertive behavior among clock sources with same QL value
and always selects the signal with the best QL value. For clock option 1, the default is revertive and for
clock option 2, the default is non-revertive.
The clock selection process works in the QL enabled and QL disabled modes. When multiple selection
processes are present in a network element, all processes work in the same mode.
QL-enabled mode
In the QL-enabled mode, the following parameters contribute to the selection process:
Quality level
Signal fail via QL-FAILED
Priority
External commands.
If no external commands are active, the algorithm selects the reference (for clock selection) with the
highest quality level that does not experience a signal fail condition.
If multiple inputs have the same highest quality level, the input with the highest priority is selected.