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B-24 GB1400 User Manual
Likewise, the BERT’s clock-recovery circuit must tolerate at least as much jitter as the system’s recovery
circuit without causing errors.
Although the BERT clock source should be essentially jitter-free to test the digital transmission system
under normal conditions, users may wish to stress the system at times. In that case, the BERT must
generate controlled jitter. To do so, some BERTs have a jitter generator that can sinusoidally modulate the
phase of the clock source.
On the receive end, the BERT monitors the effect of the controlled jitter in two ways: First it looks for an
increased error rate, then it measures the jitter remaining in the recovered data. The second measurement
yields the system’s jitter-transfer function. The jitter-measurement circuit can also be used without the
jitter generator to measure the system’s own jitter.
The BERT transmitter’s principal task is to send a data pattern to the transmission system. The most
general scheme is a repeating pattern that can be as short as 8 bits or as long as thousands of bits. Users
can design the pattern to exercise the system in a number of ways, including noise margin and clock-
recovery stressing.
Noise-Margin Stressing
The quality of signal F determines whether the digital transmission system decides correctly between a
logic 1 and a logic 0. That quality depends on the noise margin, which is the separation between F and the
logic threshold at the sampling point. Any distortion (usually due to a nonflat frequency response in the
linear channel) reduces the noise margin. If the noise margin is large, the error rate is essentially zero and
doesn’t indicate the margin.
A BERT, however, can measure the noise margin by reducing it in a controlled way until the error rate is
significant. The measurement uses what’s called baseline wander. Most transmission systems are AC
coupled to suppress the effects of biasing and DC offsets (see the following figure).