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GB1400 User Manual I-1
Theory of Operation
See block diagrams of GB1400 TX and GB1400 RX at end of this section.
GB1400 Generator (TX)
Design Overview
The GB1400 TX is designed to generate a programmable WORD of 16-bits , and
five PRBS of 2
n-1
(n=7, 15, 17, 20, 23), at serial data rates of up to 1400 Mb/s.
The unit incorporates a programmable crystal-locked clock source that operates
at this bandwidth, and two programmable pulse output amplifiers, for both Clock
and Data Output.
Very high frequency GaAs, ECL and discrete circuitry is incorporated on
multilayer controlled impedance printed circuit boards. RF shielding and
critically timed coaxial cables provide wideband operation with sub-nanosecond
timing. An embedded CPU controls the programmable clock source, high-speed
data generator hardware, programmable WORD loading, remote RS-232C and
GPIB interfaces, and soft front panel control.
PLL Clock Source PCB
The PLL Clock Source PCB contains the circuitry to generate and distribute the
internal clock signals. The clock source consists of a PLL (Phase Locked Loop)
controlling two VCOs (Voltage Controlled Oscillator). A microprocessor
programs the loop prescale divider ratios.
Data Generator PCB
The Data Generator PCB contains the circuitry required to generate the PRBS
pattern, programmable WORD, clock distribution, error inject circuitry, and
pattern sync generator.
The PRBS data generator utilizes a pattern dependent, n-length shift register
(where of 2
n-1
) with modulo-2 feedback, to generate the desired PRBS pattern.
The shift register operates at 1/2 the system clock frequency. The half-rate data is
split into two phase shifted rails - one is reference, the other is delayed half a
frame. These two rails are available at the rear panel, as "Phase A", and "Phase
B". Internally they are multiplexed together to generate the full rate data output.
The programmable WORD is level shifted from TTL to ECL and loaded into
ECL registers, then multiplexed and clocked out in a serial stream at full-rate.
The 16-bits are loaded at full rate, allowing immediate change to the data pattern.
In PRBS mode, the Pattern Sync circuit detects the start (n, 1, zeros) of the PRBS
pattern. This produces a single bit width pulse once per pattern frame. In WORD
mode, the shift register detects the programmable WORD load pulse, which
occurs once per WORD frame.