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GB1400 User Manual D-5
Standard Event Status Enable Register
Different conditions within the Standard Event Status Register can be individually
enabled or disabled. The Standard Event Status Enable Register contains enabling
bits. Each time one of the event conditions or one of the enabling bits change, the
status of the ESB bit is re-evaluated. If any status bit is set and its corresponding
enable bit is set, the ESB bit is set also.
Each time the GB1400 is powered on, this byte is reset so that no bits are
enabled. The bit definition for the Standard Event Status Enable Register is the
same as it is for the Standard Event Status Register.
Test Status Event Register (Analyzer only)
The TSB bit is the summary of the Test Status Event Register. This byte has an
enabling byte which works in a similar manner to the above Status Byte. The
individual bits within the Test Status Event Register represent the different
conditions which might cause a Test Event. The bit definitions for the Test Status
Event Register are as follows.
Bit 1 End-of Window
condition
Set at the end of each window period
Bit 2 End-of-Test condition Set at the end of each Test
Bit 3 Threshold Error
condition
Set whenever Test is running and Errored
Second occurs, where error rate is above Test
Error Rate Threshold
Bit 4 Synchronization Loss
condition
Set whenever SYNC LOSS occurs
Bit 5 Phase Error condition Set whenever a Phase Error occurs
Bit 6 Auto Synchronization
complete
Set whenever AUTO SEARCH locks on a Data
Pattern
Bit 7 Not Used
Bit 8 Not Used
Test Status Event Enable Register (Analyzer only)
The different conditions within the Test Status Event Register can be individually
enabled and disabled. The Test Status Event Enable Register contains enabling
bits. Each time one of the event conditions or one of the enabling bits change, the
status of the TSB bit is re-evaluated. If any status bit is set and its corresponding
enable bit is set, the TSB bit will set. Each time the GB1400 is powered on, this
byte is reset so that no bits are enabled. The bit definition for the Test Status
Event Enable Register is the same as for the Test Status Event Register.